0.4 2005-01-26
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corrected td_format.c to recognize ignore pixels correctly
added config und faormat file for Schematic-wire-module-plan-4

0.3 2004-09-01
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output packets contain entire bytes, ordered by ser_no first
pixel values are converted in one step
cpu load is acceptable

0.2 2004-09-01
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output packets contain entire bytes, ordered by ser_no first
pixel values are still converted in two steps for structure of program
cpu load is tolerable

0.1 2004-08-31
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output packets contain bits as needed by devices
bit shifting results in very high cpu load
